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fn8569 rev 3.00 page 1 of 12 march 7, 2014 fn8569 rev 3.00 march 7, 2014 isl91117 high efficiency synchronous boos t converter with 4.2a switches a nd output disconnect datasheet the isl91117 is a highly-integrated boost switching regulator for battery powered applications. the device provides a power supply solution for products using dual-cell or three-cell alkaline, nicd or nimh, or one-ce ll li-ion or li-polymer battery. this device is capable of deliver ing an output current of 1.5a with pvin = 3.3v and vout = 5v. the use of a synchronous rectifier maximizes efficiency at high loads. no-load quiescent current of only 35a optimizes efficiency under light-load conditions. forced pwm and/or sy nchronization to an external clock may also be selected for noise sensitive applications. the isl91117 is designed for standalone applications and supports 5v fixed output voltag e or variable output voltages with an external resi stor divider. power su pply solution size is minimized by a 2.34mm x 1.72mm wlcsp and a 2.6mhz switching frequency, which allows for the use of tiny, low-profile inductors and ceramic capacitors to minimize the size of the solution. related literature ? an1918 , ISL91117II7-EVZ, isl91117iia-evz evaluation boards features ? input voltage range: 1.8v to 4.8v ? fixed 5v or adjustable output ? output current: up to 1.5a (pvin = 3.3v, vout = 5v) ? high efficiency: up to 96% ? 35a quiescent current maximizes light-load efficiency ? true input-output disconnect when disabled ? 2.6mhz switching frequency minimizes external component size ? selectable forced-pwm mode and external synchronization ? fully protected for short-circuit, over-temperature and undervoltage ? small 2.34mm x 1.72mm wlcsp applications ? smart phones and tablets ? wireless communication devices ? products including portable hdmi and usb-otg figure 1. typical fixed output application figur e 2. efficiency vs load current (vout = 5v) vout fb c2 2x22f pvin vin = 1.8v to 4.8v vin mode en c1 22f isl91117 gnd pgnd lx blkg l1 1h vout = 5v 50 55 60 65 70 75 80 85 90 95 100 0.1 1 10 100 1000 load current (ma) efficiency (%) vin = 2.7v vin = 3.0v vin = 3.6v vin = 4.2v
isl91117 fn8569 rev 3.00 page 2 of 12 march 7, 2014 block diagram pin configuration isl91117 (4x5 wlcsp) top view osc error amp pvin pwm control pvin monitor blkg v ref ref reverse current vout b1 b2 b4 lx gate drivers & anti- shoot thru d1 vin thermal shutdown current detect b5 vout monitor d2 en d5 fb b3 pgnd d4 gnd en en en en vout clamp c1 d3 mode c3 voltage prog. en soft discharge a1 c2 a2 c4 a4 a5 c5 a3 blocking fet pwm comp a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 c1 c2 c3 c4 c5 d1 d2 d3 d4 d5 pin descriptions pin # pin names description a5, b5, c5 vout boost output. connect 2x22f capacitor to pgnd. a4, b4, c4 lx switching node of the boost converter. a3, b3, c3 pgnd power ground for high switching current. a2, b2, c2 blkg blocking fet terminal. connect the input side of the inductor. a1, b1, c1 pvin power input. range: 1.8v to 4.8v. connect a 22f capacitor to pgnd. d1 vin supply input. range: 1.8v to 4.8v. d2 en logic input, drive high to enable device. d3 mode logic input, high for auto pfm mode. low for forced pwm operation. also, this pin can be used with an external clock sync input. range: 2.75mhz to 3.25mhz. maximum voltage on this pin should be limited to vin. d4 gnd analog ground pin. d5 fb voltage feedback pin.
isl91117 fn8569 rev 3.00 page 3 of 12 march 7, 2014 ordering information part number (notes 1, 2, 3) part marking vout (v) temp range (c) package (pb-free) pkg. dwg. # isl91117ii7z-t (note 4) gaxc 5 -40 to +85 20 ball wlcsp w4x5.20f isl91117ii7z-t7a (note 4) gaxc 5 -40 to +85 20 ball wlcsp w4x5.20f isl91117iiaz-t gaxb adj. -40 to +85 20 ball wlcsp w4x5.20f isl91117iiaz-t7a gaxb adj. -40 to +85 20 ball wlcsp w4x5.20f ISL91117II7-EVZ (note 4) evaluation board for isl91117ii7z isl91117iia-evz evaluation board for isl91117iiaz notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free wlcsp and bga packaged products employ special pb-free material sets; molding compounds/die attach mat erials and snagcu - e1 solder ball terminals, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free wlcsp and bga packaged products are msl classified at pb-free pe ak reflow temperatures that meet or exceed the pb-free requirem ents of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl91117 for more information on msl please see techbrief tb363 . 4. contact intersil for availability.
isl91117 fn8569 rev 3.00 page 4 of 12 march 7, 2014 absolute maximum rating s thermal information pvin, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v lx (note 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v fb (isl91117iiaz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v fb (isl91117ii7z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v mode/sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin+0.3v gnd, pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . .2.5kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 200v latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 20 ball wlcsp (notes 5, 6). . . . . . . . . . . . . 66 1.0 maximum junction temperature (plastic package) . . . . . . . . . . . .+125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8v to 4.8v load current range (dc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 1.5a caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 6. for ? jc , the ?case temp? location is taken at the package top center. 7. lx pin can withstand switching transients of -1.5v for 100ns, and 7v for 20ms. analog specifications vin = pvin = en = 3.6v, vout = 5v, l1 = 1h, c1 = 22f, c2 = 2 x 22f, t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c and input voltage range (1.8v to 4.8v). symbol parameter test conditions min (note 8) typ max (note 8) units power supply vin input voltage range 1.8 4.8 v v uvlo vin undervoltage lockout threshold rising 1.725 1.775 v falling 1.550 1.650 v i vin vin supply current pfm mode, no external load on vout (note 9) 27.5 60 a i sd vin supply current, shutdown en = gnd, vin = 3.6v 0.4 1.0 a output voltage regulation output voltage accuracy i out = 0ma, pwm mode -2 +2 % i out = 1ma, pfm mode -3 +4 % v fb fb pin voltage regulation for adjustable output version (isl91117iiaz) 0.788 0.80 0.812 v i fb fb pin bias current for adjustab le output version (isl91117iiaz) 0.2 a ? vout/ ? vin line regulation, pwm mode i out = 500ma, mode = gnd, vin step from 2.3v to 4.8v 0.005 mv/mv ? vout/ ? i out load regulation, pwm mode vin = 3.7v, mode = gnd, iout step from 0ma to 500ma 0.005 mv/ma ? vout/ ? vin line regulation, pfm mode i out = 100ma, mode = vin, vin step from 2.3v to 4.8v 12.5 mv/v ? vout/ ? i out load regulation, pfm mode vi n = 3.7v, mode = vin, i out step from 0ma to 100ma 0.4 mv/ma v clamp output voltage clamp rising 5.25 5.95 v output voltage clamp hysteresis 400 mv dc/dc switching specifications f sw oscillator frequency 2.4 2.6 2.9 mhz t onmin minimum on time 80 ns i nfetleak lx pin leakage current -0.5 +0.5 a
isl91117 fn8569 rev 3.00 page 5 of 12 march 7, 2014 soft-start and soft discharge t ss soft-start time time from when en signal asserts to when output voltage ramp starts. 1ms time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value. vin = 2v, i out = 200ma 2ms r dischg vout soft-discharge on-resistance en < vil 120 power mosfet r dson_p p-channel mosfet on-resistance i out = 200ma 90 m r dson_n n-channel mosfet on-resistance i out = 200ma 75 m i pk_lmt p-channel mosfet peak current limit 3.7 4.2 4.7 a pfm/pwm transition load current threshold, pfm to pwm 200 ma load current threshold, pwm to pfm 75 ma external synchronization frequency range 2.75 3.25 mhz thermal shutdown 150 c thermal shutdown hysteresis 35 c logic inputs i leak input leakage 0.03 0.5 a v ih input high voltage 1.4 v v il input low voltage 0.4 v notes: 8. parameters with min and/or ma x limits are 100% tested at +25c, unless otherw ise specified. temperature limits established by characterization and are not production tested. 9. quiescent current measurements are ta ken when the output is not switching. analog specifications vin = pvin = en = 3.6v, vout = 5v, l1 = 1h, c1 = 22f, c2 = 2 x 22f, t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c and input voltage range (1.8v to 4.8v). (continued) symbol parameter test conditions min (note 8) typ max (note 8) units
isl91117 fn8569 rev 3.00 page 6 of 12 march 7, 2014 typical performance curves figure 3. maximum output current vs input voltage (v out = 5v) figure 4. efficiency vs load current (vout = 5v, mode = low, t a = +25c) figure 5. efficiency vs in put voltage (mode = high, t a = +25c) figure 6. input current vs input voltage (mode = high) figure 7. input current vs input voltage (mode = low) figure 8. output voltage vs load current (mode = high, t a = +25c) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 vin (v) maximum output current (a) 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 load current (ma) efficiency (%) vin = 2.7v vin = 3.6v vin = 3.0v vin = 4.2v 60 65 70 75 80 85 90 95 100 1.8 2.3 2.8 3.3 3.8 4.3 4.8 vin (v) efficiency (%) load = 10ma load = 500ma load = 1000ma load = 100ma 60 70 80 90 100 110 120 130 140 1.8 2.3 2.8 3.3 3.8 4.3 4.8 input current (a) vin (v) +25c -40c +85c 0 5 10 15 20 25 30 1.8 2.3 2.8 3.3 3.8 4.3 4.8 input current (ma) vin (v) +85c +25c -40c 4.94 4.95 4.96 4.97 4.98 4.99 5.00 5.01 0.1 1 10 100 1000 load current (ma) vout (v) vin = 2.7v vin = 3.0v vin = 4.2v vin = 3.6v
isl91117 fn8569 rev 3.00 page 7 of 12 march 7, 2014 figure 9. output voltage vs load current (mode = low, t a = +25c) figure 10. output voltage vs input voltage (mode = high, ta = +25c) figure 11. pfm mode operation (vin = 3.6v, vout = 5v, 10ma load) figure 12. pwm mode operation (vin = 3.6v, vout = 5v, 200ma load) figure 13. load transient (vin = 3.0v, vout = 5v) f igure 14. load transient (vin = 3.0v, vout = 5v) typical performance curves (continued) 4.90 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5.00 1 10 100 1000 load current (ma) vout (v) vin = 2.7v vin = 3.0v vin = 4.2v vin = 3.6v 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 1.8 2.3 2.8 3.3 3.8 4.3 4.8 vin (v) vout (v) load = 10ma load = 500ma load = 100ma load = 1000ma lx ? (5v/div) inductor ? current ? (500ma/div) vout, ? 5v ? offset ? (20mv/div) timescale ? (2s/div) lx ? (5v/div) inductor ? current ? (500ma/div) vout, ? 5v ? offset ? (20mv/div) timescale ? (0.5s/div) vin ? (1v/div) load ? current ? (20ma/div) vout, ? 5v ? offset ? (50mv/div) timescale ? (200s/div) 0ma ? ? ? 50ma load ? transient vin ? (1v/div) inductor ? current ? (1a/div) vout, ? 5v ? offset ? (200mv/div) timescale ? (200s/div) 10ma ? ? ? 1a ? load ? transient (240ma/s ? slew ? rate)
isl91117 fn8569 rev 3.00 page 8 of 12 march 7, 2014 figure 15. line transient (vout = 5v) figure 16. line transient (vout = 5v) figure 17. start-up with no load (vin = 3.6v, vout = 5v) figure 18. start-up with 25 ? (vin = 3.6v, vout = 5v) typical performance curves (continued) vin ? (1v/div) vout, ? 5v ? offset ? (100mv/div) timescale ? (500s/div) 4.2v ? ? ? 3.6v line ?? transient vin ? (1v/div) vout, ? 5v ? offset ? (200mv/div) timescale ? (1ms/div) 3.8v ? ? ? 3.2v line ?? transient en ? (2v/div) vout ? (1v/div) timescale ? (500s/div) inductor ? current ? (500ma/div) en ? (2v/div) vout ? (1v/div) timescale ? (500s/div) inductor ? current ? (500ma/div)
isl91117 fn8569 rev 3.00 page 9 of 12 march 7, 2014 functional description functional overview refer to the ?block diagram? on page 2. the isl91117 implements a complete boost switching regulator, with pwm controller, internal switches, references, protection circuitry, and control inputs. internal supply and references referring to the ?block diagram? on page 2, the isl91117 provides two power input pins. the pvin pin supplies input power to the dc/dc converter, while the vin pin provides the operating voltage source required for stable v ref generation. separate ground pins (gnd and pgnd) are provided to avoid problems caused by ground shift due to the high switching currents. enable input a master enable pin en allows the device to be enabled. driving the en pin low invokes a power-down mode, where most internal device functions, including input and output power-good detection, are disabled. soft discharge when the device is disabled by driving en low, an internal resistor between vout and gnd is activated. this internal resistor has typical 120 resistance. por sequence and soft-start bringing the en pin high allows the device to power-up. a number of events occur during the start-up sequence. the internal voltage reference powers up, and stabilizes. the device then starts operating. there is a typical 1ms delay between assertion of the en pin and th e start of switching regulator soft-start ramp. the soft-start feature minimizes output voltage overshoot and input in-rush currents. during soft-start, the reference voltage is ramped up to provide a ramping vout voltage. while the output voltage is lower than approximat ely 20% of the target output voltage, switching frequency is reduced to a fraction of the normal switching frequency to aid in producing low duty cycles necessary to avoid input in-rush current spikes. once the output voltage exceeds that threshold, switching frequency is increased to its nominal value. the soft-start time is typically 3ms. increasing the load current will increase these typical soft-start times. short circuit protection the isl91117 provides short-circuit protection by monitoring the feedback voltage. when feedback voltage is sensed to be lower than a certain threshold, the pwm oscillator frequency is reduced in order to protect the device from damage. the p-channel mosfet peak current limit remains active during this state. undervoltage lockout the undervoltage lockout (uvlo) feature preven ts abnormal operation in the event that the supply voltage is too low to guarantee proper operation. when the vin voltage falls below the uvlo threshold, the re gulator is disabled. thermal shutdown a built-in thermal protection feature protects the isl91117 if the die temperature reaches +150c (typical). at this die temperature, the regulator is completely shut down. the die temperature continues to be monitored in this thermal-shutdown mode. when the die temperature falls to +125c (typical), the device will resume normal operation. when exiting thermal shutdown, the isl91117 will execute its soft-start sequence. external synchronization an external sync feature is provid ed. applying a clock signal with a frequency between 2.75mhz and 3.25mhz at the mode input, forces the isl91117 to synchronize to this external clock. the mode input supports standard logic levels. pwm operation the control scheme of the device is based on the peak current mode control, and the control lo op is compensated internally. the peak current of the n-channel mosfet switch is sensed to limit the maximum current flowing through the switch and the inductor. the control circuit includes ramp generator, slope compensator, error amplifier, pwm comparator (see ?block diagram? on page 2). the ramp signal is derived from the inductor current. this ramp signal is then compared to the error amplifier output to generate the pwm gating signals for driving both n-channel and p-channel mosfets. the pwm operation is initialized by the clock from the internal oscillator (typical 2.6m hz). the n-channel mosfet is turned on at the beginning of a pwm cycle, the p-channel mosfet remains off, and the current star ts ramping up. when the sum of the ramp and the slope compensator output reaches the error amplifier output voltage, the pwm comparator outputs a signal to turn off the n-channel mosfet. here, both mosfets remain off during the dead-time interval, and then the p-channel mosfet is turned on and remains on until th e end of this pwm cycle. during this time, the inductor current ramps down until the next clock. at this point, following a short dead time, the n-channel mosfet is again turned on, repeating as previously described. pfm operation the boost converter enters the pf m mode of operation under light load conditions. wh en the inductor current is sensed to cross zero, the converter enters pfm mode. in this mode, each pulse cycle is still synchronized by the pwm clock. the n-channel mosfet is turned on at the rising edge of the clock and turned off when the inductor peak current reaches a certain current limit. then the p-channel mosfet is turned on, and it stays on until the inductor current goes to zero. subsequently, both n-channel and p-channel mosfets are turned off until the ne xt clock cycle starts, at which time the n-channel mosfet is turned on again. in most operating conditions, ther e will be multiple pfm pulses to charge up the output capacito r. in addition to the inductor current limit for pfm operation, the pfm pulses are also controlled by output voltage. th ese pulses continue until vout
isl91117 fn8569 rev 3.00 page 10 of 12 march 7, 2014 has achieved the upper thresh old of the pfm hysteretic controller. switching then stops, and remains stopped until vout decays to the lower threshold of the hysteretic pfm controller. applications information component selection the fixed-output version of the isl91117 requires only three external power components to implement the boost converter: an inductor, an input capacitor, and an output capacitor. the adjustable isl91117 versio ns require three additional components to program the output voltage. two external resistors program the output volt age, and a small capacitor is added to improve stab ility and response. output voltage programming, adjustable version setting and controlling the outp ut voltage of the isl91117iiaz (adjustable output version) can be accomplished by selecting the external resistor values. equation 1 can be used to derive the r1 and r2 resistor values: when designing a pcb, include a gnd guard band around the feedback resistor network to reduce noise and improve accuracy and stability. resistors r1 and r2 should be positioned close to the fb pin. feed-forward capacitor selection a small capacitor (c3 in figure 19) in parallel with resistor r1 is required to provide the specified load and line regulation. the suggested value of this capacitor is 22pf for r1 = 320k . an npo type capacitor is recommended. non-adjustable version fb pin connection the fixed output version of the isl91117 does not require external resistors or a capacitor on the fb pin. simply connect vout to fb, as shown in figure 20. inductor selection an inductor with high frequency core material (e.g., ferrite core) should be used to minimize core losses and provide good efficiency. the inductor must be able to handle the peak switching currents without saturating. a 1h inductor with 4a saturation current rating is recommended. select an inductor with low dcr to provide good efficiency. in applications where radiated noise must be minimized, a toroidal or shielded inductor can be used. pvin and vout capacitor selection the input and output capacitors sh ould be ceramic x5r type with low esl and esr. the recommended input capacitor value is 22f. the recommended vout capacitor value is 2x22f or 47f. figure 19. typical isl91117iiaz application c2 2x 22f vout = 5v 320k 60.4k c3 22pf r1 r2 vout fb pvin vin mode en c1 22f isl91117 gnd pgnd lx blkg l1 1h vin = 1.8v to 4.8v v out 0.8v 1 r1 r2 ------- - + ?? ?? ? = (eq. 1) table 1. inductor vendor information manufacturer series website coilcraft xfl4020-102me www.coilcraft.com murata lqh5bpn1r0nt0 www.murata.com table 2. capacitor vendor information manufacturer series website avx x5r www.avx.com murata x5r www.murata.com taiyo yuden x5r www.t-yuden.com tdk x5r www.tdk.com figure 20. typical isl91117ii7z application vout fb c2 2x 22f pvin vin = 1.8v to 4.8v vin mode en c1 22f isl91117 gnd pgnd lx blkg l1 1h vout = 5v
fn8569 rev 3.00 page 11 of 12 march 7, 2014 isl91117 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2014. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. recommended pcb layout correct pcb layout is critical for proper operation of the isl91117. the input and output capacitors should be positioned as closely to the ic as possible. the ground connections of the input and output capacitors should be kept as short as possible, and should be on the component layer to avoid problems that are caused by high switching currents flowing through pcb vias. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support figure 21. recommended layout revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change march 7, 2014 fn8569.3 updated related literature. figure 18 on page 8 title changed from start-up with no load (vin = 3.6v, vout = 5v) to start-up with 25 ? (vin = 3.6v, vout = 5v). february 4, 2014 fn8569.2 initial release.
isl91117 fn8569 rev 3.00 page 12 of 12 march 7, 2014 package outline drawing w4x5.20f 20 ball wafer level chip scale package (wlcsp 0.4mm pitch) rev 0, 5/13 notes: dimensions and tolerance per asme y 14.5m - 1994. dimension is measured at the maximum bump diameter parallel to primary datum z . primary datum z and seating plane are defined by the spherica l crowns of the bump. bump position designation per jesd 95-1, spp-010. there shall be a minimum clearance of 0.10mm between the edge of the bump and the body edge. 3. 2. 4. 1. 5. bottom view top view side view recommended land pattern 1.720.030 2.3350.030 pin 1 (a1 corner) (4x) 0.10 x y 1.200 0.400 20x 0.2650.035 1.600 0.3675 0.260 0.200 abcd 1 2 3 4 5 package outline 0.290 0.400 0.240 0.040 bsc (backside coating) seating plane 3 z 0.05 z 0.2650.035 x20 zxy z 0.10 0.05 m m 0.2000.030 0.5400.050

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